Silicon-on-lnsulator (SOI) technology has been around since the 1960s when so-called silicon on sapphire (SOS) was first introduced. Silicon on sapphire has been used for many years for the fabrication of spaceborne and high-speed integrated circuits. It is still used in the fabrication of radio-frequency circuits.

More recent SOI materials involve only silicon and silicon dioxide—the two most common materials used in the fabrication of integrated circuits—as opposed to SOS, which requires the use of an alumina substrate.

Silicon-on-insulator technology has been used for a long time in niche applications such as spacecraft electronics and devices operating in a hightemperature or radiative environment. Recently however much attention has been paid to SOI technology because it is extremely suitable for the fabrication of low-voltage integrated circuits. Such circuits are in high demand for all kinds of portable systems, ranging from cellular phones to laptop computers. In August of 1998, IBM, Sharp, and other semiconductor manufacturers announced the development of SOI chips for high-speed computing and telecommunication con-sumer electronics. Most major semiconductor companies are putting considerable effort into SOI-circuit development for mainstream low-power applications.

In silicon-on-insulator (SOI) technology, devices are dielectrically insulated from one another—usually by silicon dioxide. Unlike in conventional silicon devices, there is no direct contact between a transistor and the silicon substrate. The advantages of this type of isolation are many: reduced parasitic capacitances and reduced crosstalk between devices, improved current drive, subthreshold characteristics, and current gain. Silicon-on-insulator devices have been and are being used in several niche-market applications such as hightemperature and radiation-hard integrated circuits. However most importantly, SOI technology seems perfectly adapted to the needs of low-voltage, low-power (LVLP) electronic circuits. Because of the growing market for portable systems, LVLP technology is bound to soon become one of the drivers of the microelectronics industry, and SOI is likely to be part of it. Moreover major companies such as IBM, Sharp, Motorola, and Peregrine have announced upcoming lowpower and high-frequency lines of SOI products. The goal of this article is to introduce the reader to the basics of SOI device physics and the integrated-circuit applications of SOI.

Watanabe and Tooi first reported on the formation of silicon oxide by oxygenion implantation into silicon in 1966. Further investigations of such oxygen-implanted oxide layers have been carried out by several workers, with the result that the oxide has equivalent isolation characteristics to those for thermally grown silicon oxide. Practical applications of the oxygen-implanted oxide to semiconductor devices have been reported by only a few workers, with a suggestion of their usefulness. Unfortunately Watanabe and Tooi's work has not been followed by additional silicon-on-insulator (SOI) studies.

In 1978 Izumi, Doken, and Ariyoshi succeeded in fabricating a complementary-metal-oxide-semiconductor (CMOS) ring oscillator using a buried SiO2 layer formed by oxygenion (16O+) implantation into silicon. They named the new SOI technology “SIMOX,” which is short for separation by implanted oxygen. Since then Izumi and his research group have continued their study of SIMOX technology.

Oxygen-implanted silicon-on-insulator (SOI) material, or SIMOX (separation by implantation of oxygen), is another chapter in the continuing development of new material technologies for use by the semiconductor industry. Building integrated circuits (ICs) in a thin layer of crystalline silicon on a layer of silicon oxide on a silicon substrate has benefits for radiationhard, high-temperature, high-speed, low-voltage, and low-power operation, and for future device designs. Historically the first interest in SIMOX was for radiation-hard electronics for space, but the major application of interest currently is low-power, high-speed, portable electronics. Silicon-on-insulator also avoids the disadvantage of a completely different substrate such as sapphire or gallium arsenide. Formation of a buried-oxide (BOX) layer by high-energy, high-dose, oxygen ion implantation has the advantage that the ion-implant dose can be made extremely precise and extremely uniform. However the silicon and oxide layers are highly damaged after the implant, so high-temperature annealing sequences are required to restore devicequality material. In fact SIMOX process development necessitated the development of new technologies for high-dose implantation and high-temperature annealing.

“Wafer bonding” refers to the phenomenon in which mirror-polished, flat, and clean wafers of almost any material—when brought into contact at room temperature—are locally attracted to each other by van der Waals forces and adhere or “bond” to each other. Wafer bonding is alternatively also known as “direct bonding” or “fusion bonding,” or more colloquially as “gluing without glue.” Although this is by no means required, in most cases, the wafers involved in actual applications are typical semiconductor wafers consisting of single-crystalline material used in microelectronics or optoelectronics such as silicon or gallium arsenide.

In a silicon-on-insulator (SOI) structure, a thin layer of monocrystalline silicon rests on a dielectric layer—generally amorphous—itself on a silicon wafer. Because such a structure cannot be achieved by conventional methods, different ways had to be imagined to facilitate its construction.

The basic physics phenomenon that led the author to invent the process generally known under the name of Smart-Cut® is blistering. Blistering (Figure 1), in addition to flaking and exfoliation, is a visible macroscopic effect that has been known for a long time and is induced by high-dose implantations of inert gas or hydrogen ions in materials. These macroscopic effects result from the cooperative result of the microscopic effects induced in depth by penetration of particles. The microscopic effects of hydrogen or rare-gas implantation such as creation of microcavities, microblisters, or microbubbles (close to the penetration depth Rp corresponding to the maximum concentration) have been known for a long time. These microcavities enhance propagation of intercavity fractures where their density (depending on statistical fluctuations) reaches a percolation threshold. This leads to formation of a local cluster where all the microcavities are joined by a fractured zone, resulting in a blister at the surface. The driving force of this mechanism is the gas pressure in the microcavities and the stresses in the layer.

An integrated substrate, consisting of more than one material or material structure, is highly desirable for optimizing performance of multiple-device types on a single chip or for growing high-quality heteroepitaxial films on compliant substrates. A typical integrated substrate contains a stack of thin layers of similar or dissimilar materials that are either amorphous, or poly- or single-crystalline with a variety of lattice constants or crystallographic orientations. Partially or fully processed device layers can also be transferred onto a desired substrate where the transferred device layer can be further processed on the opposite side of its original surface. In this article, we focus on issues related to layer transfer for material integration.

Layer transfer from a hydrogen (H)-implanted wafer onto a desired substrate by wafer bonding and layer splitting (the so-called “Smart-Cut®” method) is an attractive approach to prepare integrated materials, such as-silicon-on-insulator (SOI), SiC or GaAs on oxidized silicon, and Ge on glass.