In this paper, we describe the design, layout, and performance of a 6-bit TTD (true time delay) chip operating over the entire band of 2–18 GHz. The 1.15 mm2 chip is implemented using TSMC foundry 65 nm technology. The least significant bit is 1 ps. The design is based on the concept of all-pass network with some modifications intended to reduce the number of unit cells. Thus, the first three bits are implemented in a single delay cell. A peaking buffer amplifier between bit 4 and bit 5 is used for impedance matching and partial compensation of the insertion loss slope. The rms delay error of the TTD is <1 ps over most of the frequency band and insertion loss is between 2.5 and 6.3 dB for all 64 states.

A highly integrated Ku-band (10.7–12.75 GHz) planar phased array receiver of 64 antenna elements is presented. It features instantaneous reception of the full Ku-band (2.05 GHz wide) in two orthogonal polarizations with wide scan angles by using time delay instead of phase shift. The receiver is part of a system for satellite broadcast TV reception on board of moving vehicles. Two SiGe radio frequency integrated circuits (RFICs) were developed, packaged in ceramic BGAs and assembled onto a 15-layer printed circuit board (PCB) which integrates the antenna elements. An outline of the system is given along with a detailed description. It sets a new standard in integration density. The receiver has extensive analog signal processing at intermediate frequency (IF)-level. A novel bipolar implementation for true time delay is proposed, with a continuous programmable delay range of 0…80 ps with less than 2.5 ps group-delay variation in 2 GHz bandwidth (BW). The wide BW calls for a constant group-delay implementation in the IF chain. The receiver (RFIC) consumes only 132 mW per channel. Each channel has 40 dB gain.

This paper proposes a technique to design wide band switched-line (SL) true-time-delay (TTD) networks, commonly used for phased array antenna (PAA) applications. This study investigates the constant-delay behavior of switched-line phase shifters based on single-pole double-throw (SPDT) switches. Circuit sizing starts by considering the effective S-parameters of the switches, to use their non-idealities as an integral part of the phase shift linearly dependent to the frequency and by considering, from the beginning, the possible spatial positioning of elements that allows the circuit feasibility as a design target. The aim of this study is to provide a technique suitable for the design of well-matched TTD networks with a flat delay in wide bandwidth. In this paper, we propose new design formulas for which we show a single-frequency implementation. A computational strategy is used to obtain numerical solutions of the derived equations with this study. Finally, a monolithic X-band TTD circuit example is shown.