With the evolution of 5G and 6G network architectures, the demand for highly compact system-on-chip-based devices with high data transfer capabilities has been increased significantly. While the advancement of very large-scale integration technology with the continuous scaling of complementary metal–oxide–semiconductor nodes put forward to integrate different functional modules of a complete system on a single IC board, the antenna being the largest component still remains outside of the chip. Integration of the antenna and other functional modules of a system on the same chip leads to produce a really compact and economical design. Though on-chip antenna (OCAs) have several other advantages and emerging applications, they have some design challenges in terms of low gain due to losses in the substrate, requirement of miniaturization at lower microwave frequencies (LMFs) (particularly, below 10 GHz), unavailability of proper design rules, etc. In this paper, analyzing the design challenges of OCAs, their current research trends and future perspective applications are discussed.

This paper presents the design and analysis of a miniaturized, coplanar waveguide-fed ultra-wideband monopole on-chip antenna with band-notch characteristics. By incorporating a “U”-shaped slot in the feedline, a band-notch is realized in the frequency range of 7.9–8.4 GHz to avoid interference from the X-band uplink satellite communication system. The proposed antenna achieved good voltage standing wave ratio (VSWR) characteristics with VSWR value <2 for the frequency range of 2.5–20.1 GHz excluding the band-notched frequencies. The fractional bandwidth and bandwidth ratio are obtained as 156% and 8.04:1, respectively. Dominant factors that affect the center frequency and bandwidth of the notched band are thoroughly investigated. This paper addresses both frequency as well as time domain behavior of the proposed structure. Standard 675 µm thick, high resistive silicon substrate (ρ≥8 kΩ-cm, εr = 11.8, and tan δ = 0.01) is used to design the proposed compact antenna structure with a layout area of 8.5 × 11.5 mm2. Fabrication process steps along with simulated and measured data are presented here. A close analogy between simulated and measured data is observed.

This paper presents a cavity-backed dual-slot antenna in 0.13-μm SiGe BiCMOS technology. The dual-slot structure is excited by a cross-shaped strip line and a cavity which is formed by the topmost metal layer connected to the bottom metal layer through vias in between. By adopting dual-slot and cross-shaped feed line, the bandwidth is significantly enhanced by 196% compared with the single-slot antenna with straight feed line. The reason for bandwidth enhancement has been analyzed. The proposed antenna shows a measured impedance bandwidth of 15.2 GHz from 248.2 to 263.4 GHz for |S11| < −10 dB. The simulated and measured peak gains of the cavity-backed dual-slot antenna are −1.3 and −2.1 dBi, respectively. The simulated radiation efficiency is 31.1%. The total size of the antenna is 0.46 mm × 0.48 mm.

This paper describes the analysis and the design of an integrated antenna on 0.13 µm SiGe BICMOS technology. A non-resonant dipole antenna integrated on SiGe is electromagnetically coupled to a radiating element reported on a printed circuit board (PCB) substrate. This integrated solution, also compatible with system in package (SIP) concept, provides significant improvements with respect to direct System On Chip (SoC) integration. The main objective of this SIP antenna lies on the optimization of integrated millimeter wave front-ends modules, considering the immediate antenna environment (especially the lossy substrate and technological dielectric/metallic levels), in order to achieve performances compatible with short range radar specifications at 79–81 GHz. One solution, using a RT/Rogers Duroid 6006 PCB (er = 6, thickness h = 127 µm), is presented, providing a 2.93 dBi gain, and 45% radiation efficiency antenna.