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Chip Surface Damage Induced by Internal Stress of Lead–ON–Chip (Loc) Packages

Published online by Cambridge University Press:  22 February 2011

Masazumi Amagai  and
Eiji Kawasaki
Masazumi Amagai
Affiliation:
Texas Instruments Japan Limited, Hiji Plant, New Package Development 4260 Takao, Kawasakiaza, Ohaza, Hiji, Hayami, Oita 879–15, Japan
Eiji Kawasaki
Affiliation:
Texas Instruments Japan Limited, Miho Plant, Wafer Fab Engineering 2350 Kihara, Miho, Inashikigun, Ibaraki 300–04, Japan
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Abstract

In lead–on–chip (LOC) packaging technology, the lead fingers are attached directly to the surface of the chip using a double–side adhesive tape. This method of chip attachment naturally concerns with regards to stress on the polyimide coated chip surface. Device failure related to fracture in the passivation layers and the Al–Si metal has been observed in temperature cycle tests. The dominant issue is polyimide cracking due to mechanical stress caused by internal stress of LOC packages. To investigate the effect of polyimide characterization, devices were fabricated with different polyimides. The degree of polyimide cracking was determined with scanning electron microscope (SEM) technique. The polyimides were characterized with chemicals, tensile measurement tester, thermal analyzer, fourier transform infrared spectroscope (FTIR), computer simulation and various package-level reliability tests. The results of the characterization and an explanation of the primary factors affecting chip surface damage are presented in this paper.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 338: Symposium – Materials Reliability in Microelectronics IV , 1994 , 185
Copyright
Copyright © Materials Research Society 1994

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References

REFERENCES

[1] Ward, William C., “Volume Production of Unique Plastic Surface-Mount Modules for the IBM 80-ns 1-Mbit DRAM Chip by Area Wire Bond Techniques,” Proceedings of the 38th IEEE ECC, 1989 Google Scholar
[2] Hagen, D., et al., “Lead On Chip TSOP Assembly Process for Fast SRAM with Pleripherally Located Bond Pads,” Proceedings of the IEEE CIHMT Irnernatiornal Electronics Manufacturing Technology Symposium, September 1992, pp.39–47 Google Scholar
[3] Lamson, Mike, et al., “Lead-On-Chip Technology for High Performance Packaging,” Proceedings of the 1.993 IEEE ECTC, 1993, pp.1045–1050 Google Scholar
[4] Amagai, M., “Polyimide Surface Characteristics for Adhesion Strength at the Interface Between Polyimide and Mold resin,” Proceedings of the 1993 IEEE IPFA, 1993, pp.6–10 Google Scholar
[5] Ishida, H., kelley, K., Polymer 32, 1585–1588 (1991)Google Scholar