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Interfacial Film Induced Fails in Titanium Salicide Interconnections with Tungsten Vias in High Density Dram Devices

Published online by Cambridge University Press:  02 July 2020

Terence Kane
Affiliation:
IBM Analytical Services, Microelectronic Division, Hopewell Junction, NY12533
Ron Anderson
Affiliation:
IBM Analytical Services, Microelectronic Division, Hopewell Junction, NY12533
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Extract

The scalability requirements of higher and higher density DRAM and logic CMOS devices has popularized the salicide process for source to drain connections using TiSi2 and ( more recently ) CoSi2.

The desirability of these salicide processes is well documented with low sheet resistivity properties offering improved access time in DRAM and faster microprocessor speeds.

Besides the obvious drawback in temperature stability of these salicides, the irregular reaction of titanium or cobalt with silicon during RTA processing can result in irregular or “rough” surface features in the salicide. Submicron contaminants (especially metallic species) introduced during in-line electrical test of Kerf structures with high wettability are not easily dislodged by conventional aqueous/ultrasonic cleaning steps. Solvent process cleaning steps can leave residues in the irregular “rough” salicide surface leading to interfacial films between the salicide and the subsequent via connection to overlying bit lines ( or metal one lines ).

Type
Recent Developments In Microscopy For Studying Electronic and Magnetic Materials
Copyright
Copyright © Microscopy Society of America 1997

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References

Murarka, S., “Salicides for VLSI Applications”, Academic Press, New York, 1983.Google Scholar
Kenney, D., et. al., “Symposium on VLSI Technology”. Tech. Dig. 14 (1992).Google Scholar
Murarka, S.,“Salicides, Germanides and Their Interfaces”, MRS Symposium Poc. 320,1994.Google Scholar